As integrated circuit device features continue to shrink beyond 90 nm, the electrical characteristics of transistors with 90 nm and smaller gate lengths have become less than ideal. For example, leakage current and susceptibility to damage of transistor gate dielectric increases as the transistors get smaller. Further, merely using the integrated circuit results in the threshold voltage of the transistors (the voltage applied to the gate of a transistor at which the transistor begins to conduct) in the integrated circuit shifting (aging) that becomes more pronounced with smaller device dimensions. Unfortunately, the shift in threshold voltage is a significant factor in limiting the useful lifetime of an integrated circuit because the threshold voltage shift by the transistors eventually lead to the transistors possibly becoming unresponsive to signals applied to the gates thereof, leading to the functional failure of the integrated circuit.
One significant contributor to transistor threshold voltage shift is damage to the transistor due to current injection. This phenomenon is known as hot-electron injection or hot-hole injection depending if the affected transistor is an n-channel or p-channel transistor, respectively, and is referred to generically as hot-carrier injection (HCI).
HCI is a slow process during normal operation but the effect thereof is cumulative over the lifetime of the integrated circuit. Therefore, testing production integrated circuits while still in wafer form requires a technique to accelerate the effects of HCI over a relatively short time period, measuring transistor performance during the testing period, and then extrapolating from changes in the transistor performance to get a projection of the device lifetime. If the projected lifetime is less than a particular value, e.g., 15 years, the wafer is rejected for being overly susceptible to HCI. Various HCI testing techniques have been proposed and adopted, such as that described in “Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress,” JESD28A, published December 2001 (along with corresponding JESD60A for p-channel transistors, published September 2004) by JEDEC Solid State Technology Association, Arlington, Va., USA, both of which are incorporated by reference herein in their entirety. However, the JEDEC test requires multiple hours to perform, an impractical test technique for testing each wafer on a production line. Instead, statistical sampling of selected wafers is used to project device lifetimes of entire production runs (production lots). This may lead to overly optimistic lifetime estimations (with resulting high field failures) or rejecting many wafers that are otherwise satisfactory absent additional, time consuming testing, both of which are costly.